Hardware Realization of a Modified GMD Transceiver

In [7], Dr. Gerald E. Sobelman’s research group presents a MIMO joint transceiver design that can run at 350 MHz on a Xilinx Virtex-4 xc4vlx200ff1513-12 FPGA. The implementation is an 8 x 8 MIMO transceiver with a 16-QAM symbol constellation. This system can provide data throughput of 11.2 Gbps. The design is based on a modified Geometric Mean Decomposition (GMD) for a flat fading MIMO channel using VBLAST MIMO detection. The design flow uses Matlab Simulink as the model builder followed by the Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.

Hardware Realization of UWB Transceiver and Channel Model

The hardware transceiver realization design for asymmetric UWB links and the GMD-based transceiver designs are challenging due to the ultra-wide bandwidth of the signal and the low-power consumption requirement. To this end, we have developed a complete procedure for FPGA-based hardware design of the UWB transceiver and the UWB channel model [7], [10].

In [7], an enhancement to the MB-OFDM system, known as Pulsed-OFDM, has been proposed to reduce the complexity and power consumption of the transceiver without sacrificing performance. In this paper, we describe the detailed FPGA implementation of a complete Pulsed-OFDM transceiver. The resource requirements are given for each of the major blocks for an implementation using a Xilinx Virtex^TM-4 device. The entire system can be mapped onto a single FPGA chip. Our hardware architecture can readily incorporate the realization of the GMD-based transceiver for asymmetric UWB links, especially when OFDM is employed to mitigate the ISI in frequency selective fading channel.

Fig. 5. Design methodology and flow diagram.

The design methodology used to synthesize each block is shown in the Fig. 5. The algorithm of each block in the system is first verified by using Matlab with double precision floating point. After the algorithms are verified, the hardware implementations are obtained by constructing block diagrams in Simulink. For block and system simulations, this method enables us to integrate different components and validate their performance by exploring design trade-offs between different sets of parameters. VHDL and/or Verilog code can also be imported into Simulink via the Xilinx System Generator block set, which gives flexibility to the design flow. Simulink and Xilinx System Generator create bit-true and cycle-accurate hardware models which can be programmed into FPGA prototyping boards. The Xilinx Integrated Software Environment (ISE) is used as the synthesizer in the design flow diagram shown below. ModelSim can also be used to verify the hardware simulation of the blocks by using test vectors generated by the System Generator or HDL test benches. Finally synthesis and performance results of the blocks are reported using ISE, and bitstreams are generated to program the FPGA boards.

Fig. 6. Channel model architecture.

Ultra wideband (UWB) channel models [7] have been developed as Matlab code and approved by the study group IEEE 802.15.SG3a as a method to evaluate the physical layer performance. For system-level test of our GMD-based UWB transceivers, we have recently presented a digital hardware model for ultra-wideband channels, based on the design flow in Fig. 5. The system runs at 80 MHz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The complete functional block diagram can be drawn as in Fig. 6. Required digital arithmetic functions include a Gaussian noise random number (GNRN) generator (GNRNG), a division operation, a square-root computation (SQRT) and a base-two powering function (2^x). The logic utilization is 7,747 slices which consumes about half of the resources of an xc4vsx35 device. This leaves room for a transmitter and/or receiver to be implemented on the same FPGA device.

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This material is based upon work supported by the National Science Foundation under Grant No. 0621879. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.